The system provides high process temperature control (+60°C to -75°C) due to the thermal bonding of the substrate to the sample stage for ensuring good thermal contact and uniform deposition of Indium film.

Indium Thin Film Deposition using Physical Vapor Deposition (PVD)

PVD methods provide high-quality, and high-performance thin films compared to other thin film deposition methods such as electroplating. PVD coatings exhibit better adhesion, uniformity, and density, with minimal effect of environmental factors on the composition and other film properties. Moreover, PVD allows for a broader range of materials to be deposited and offers better control over coating thickness, making it suitable for applications requiring precise thickness specifications.

Indium is a ductile metal with a melting point of 156.6 °C, which is advantageous in microelectronics where lower processing temperatures are desired to prevent damage to the sensitive components. Indium's good thermal conductivity makes it suitable for applications where efficient heat dissipation is crucial such as semiconductor devices. The characteristics of indium, such as its thermal stability, and compatibility with complex crystal structures make it a valuable material for forming reliable and high-performance electrical contacts in semiconducter devices. 

Indium Solder Bump in Microelectronic Devices

A solder bump is a small, raised deposit of indium solder that is typically applied to the surface of a microelectronic device. Solder bumps are commonly used in semiconductor packaging and flip-chip bonding processes, microprocessors, integrated circuits, and other electronic components they provide an efficient and reliable method for connecting chips to substrates, allowing for high-performance and compact devices.

The indium films deposited with Icarus exhibit high-quality morphology of the film such as:

• High process temperature control (+60 °C to -75 °C) Low temperature deposition is advantageous for high shear strength and better adhesion of bump to the wafers, and it prevents lateral crystalline growth
• High yield of lift-off process due to the collimated flux that prevents coating on side walls
• 2.5h turn around time per 4μ run
• Good indium fill and high yield on shape and size of the bump array (square and round)